Electronic circuits, such as integrated circuits (ICs), are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating IC devices typically involves many steps, sometimes referred to as the “design flow.” The particular steps of a design flow often are dependent upon the type of the circuit, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators. These steps aid in the discovery of errors in the design, and allow the designers and engineers to correct or otherwise improve the design.
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, such as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. The relationships between the electronic devices are then analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.” Additionally, preliminary timing estimates for portions of the circuit are often made at this stage, using an assumed characteristic speed for each device, and incorporated into the verification process.
Once the components and their interconnections are established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various layers of material to manufacture the circuit. Typically, a designer will select groups of geometric elements representing IC components (e.g., contacts, channels, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks.
Circuit layout descriptions can be provided in many different formats. The Graphic Data System II (GDSII) format is a popular format for transferring and archiving two-dimensional (2D) graphical circuit layout data. Among other features, it contains a hierarchy of structures, each structure containing layout elements (e.g., polygons, paths or poly-lines, circles and textboxes). Other formats include an open source format named Open Access, Milkyway by Synopsys, Inc., EDDM by Mentor Graphics, Inc., and the more recent Open Artwork System Interchange Standard (OASIS) proposed by Semiconductor Equipment and Materials International (SEMI). These various industry formats are used to define the geometrical information in design layouts that are employed to manufacture integrated circuits. Once the design is finalized, the layout portion of the design can be used by fabrication tools to manufacture the circuit using a photolithographic process.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor device component could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, and the exposed areas are etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). The exposed areas then are subjected to a diffusion or ion implantation process, causing dopants, for example phosphorus, to enter the exposed epitaxial layer and form charged wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, etching, and dopants or other diffusion materials, is repeated a number of times, allowing the different physical layers of the circuit to be manufactured.
Each time that a layer of material is exposed to radiation, a mask must be created to expose only the desired areas to the radiation, and to protect the other areas from exposure. The mask is created from circuit layout data. That is, the geometric elements described in a design layout define the relative locations or areas of the circuit that will be exposed to radiation through the mask. A mask or reticle writing tool is used to create the mask based upon the design layout, after which the mask can be used in a photolithographic process.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and are placed closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the design layout onto the substrate. The diffractive effects of light often result in defects where the intended image is not accurately “printed” onto the substrate during the photolithographic process, creating flaws in the manufactured device. One or more resolution enhancement techniques (RETs) are often employed to improve the resolution of the image that the mask forms on the substrate during the photolithographic process. Examples of various resolution enhancement techniques are discussed in “Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future,” Frank M. Schellenberg, Optical Microlithography XVII, edited by Bruce W. Smith, Proceedings of SPIE Vol. 5377, which article is incorporated entirely herein by reference. One of these techniques, “optical proximity correction” or “optical process correction” (OPC), adjusts the amplitude of the light transmitted through a lithographic mask by modifying the design layout data employed to create the mask.
In a conventional OPC process, the edges of the geometric elements in the design are fragmented. For example, as shown in FIG. 3A, an edge of the geometric element 301 used to create a mask feature 300 may be fragmented into edge fragments 301A-301F, shown in FIG. 3B. The size of the edge fragments in a given layout design depends upon the OPC process parameters, often referred to as the OPC recipe. The “recipe” specifies the size of the edge fragments. While not all edges within a layout design are fragmented in every OPC process, these edges may also be referred to as edge fragments.
The model-based OPC process also simulates the printed image. That is, the photolithographic process is simulated in order to produce a simulated printed image (referred to as simulated image), such as the example image 302 shown in FIG. 3A. This simulated image is compared to the target image. Typically, this comparison is done at each edge fragment. For example, as shown in FIG. 3C, the target image is a distance d1 away from the simulated image at the edge fragment 301A, the target image is a distance d2 away from the simulated image at the edge fragment 301C, while the target image intersects the simulated image at the edge fragment 301B. The distances between the target image and the simulated image are often referred to as the edge placement error (EPE). Accordingly, in most conventional model-based OPC processes each edge fragment or unfragmented edge has an associated edge placement error (also referred to as an associated edge placement error value).
Next, the edge fragments are individually moved or adjusted in order to enable the simulated image for the resulting mask to reproduce the target image as much as possible. For example, as shown in FIG. 3D, the edge fragment 301A is displaced in a direction away from the geometric element 301, in an effort to widen the corresponding portion of the image that would be produced by the resulting mask. Similarly, the edge fragment 301C is displaced in a direction toward from the geometric element 301, in an effort to narrow the corresponding portion of the image that would be produced by the resulting mask. Next, the image that would be produced by a mask using the displaced edge fragments is simulated, and the new simulated image is compared with the target image, and the edge placement error for each edge fragment is computed.
This process of moving the edge fragments, simulating the image that would be produced using the moved edge fragments, and comparing the simulated image to the target image may be repeated a number of times. Each cycle of moving edge fragments and comparing the new simulated image to target image is referred to as an iteration of the OPC process. Typically, edge fragments moved during a given iteration, and the distance the edge fragments are displaced, are determined based upon the edge placement error. For example, because d1 is larger than d2 in FIG. 3C, a subsequent iteration of the optical proximity correction process may move edge fragment 301A a greater amount than edge fragment 301C.
The performance of an OPC process depends in part on the accuracy and predictability of lithographic process models that mathematically represent the distinct steps in the patterning sequence. These lithographic process models (sometimes also referred to as OPC models) include optical models for aerial image formation and resist/etch process models for the photoresist-associated steps such as exposure, post-exposure bake, development, and pattern transfer. The optical models for full-chip simulation are usually quasi-rigorous. For example, the Hopkins optical model may be approximated by a sum of coherent systems approximation method, which is not a dramatic simplification. By contrast, the resist/etch process models tend to be semi-empirical: mathematical formulation is used to provide a transfer function between inputs and measured outputs of interest. Due to the semi-empirical nature, the resist/etch process models need to be calibrated based on measurements on printed wafers. The model parameters are trained or calibrated so that simulation data would fit measurement data. Even some parameters for the optical models such as dose and focus may also need to be calibrated against measurement data. In a calibration process, the calibration of the optical model parameters may be performed first. With the optical model parameters thus set, a subsequent tuning of the resist model parameters is performed. Alternatively, the tuning of both the optical model parameters and the resist model parameters may be conducted simultaneously in a single lumped calibration process.
The accuracy and predictability of lithographic process models often refer to the distribution of critical dimension differences between values predicted by the models and measured values. There are two types of test structures associated with the model calibration: those for calibrating model parameters are referred to as calibration structures; and those for checking the predictability of the calibrated models are referred to as verification structures. The extent to which different varieties of calibration structures are used to calibrate model parameters affects the layout coverage of the calibrated models. Thus, the adequacy of calibration structures is important whenever the model accuracy and predictability are in question. In reality, the number of unique structures in a design is several orders of magnitude more than the number of calibration structures. Moreover, the verification process based on measurements is slow. It is thus desirable to have a quick method for evaluating and adjusting calibration structures.